1. Field of the Invention
The present invention relates to a semiconductor device and an insulated gate type bipolar transistor, having a current controlling gate electrode over a surface of a semiconductor substrate.
2. Description of the Related Art
In a power element such as an IGBT (Insulated Gate Bipolar Transistor) for a high withstand voltage and a large current, if a chip size is enlarged, a ratio of an area occupied by a withstand voltage structure (e.g., a guard ring structure), which is provided in the outer periphery of the chip, can be reduced. Further, the number of parts can be reduced to provide effects that the assembly structure can be simplified and that the cost can be reduced.
In a semiconductor wafer process for manufacturing the IGBT, on the other hand, defects may be produced by particles, for example, to cause short-circuit between an emitter and a gate. As the chip size is increased, this disadvantage becomes more liable to occur to cause a problem that a rate of non-defective products decreases.
As a technique for solving this problem, JP-A-8-191145 discloses a method for manufacturing an IGBT. In this method, the IGBT is divided into several cell blocks (gate blocks) and a wiring lead leading from each of the gate blocks to a gate bonding pad common to the gate blocks is formed with a two-layered wiring structure. In the course of the semiconductor wafer process, i.e., after first gate wiring members are formed for the respective gate blocks, the several cell blocks are determined on whether a gate and an emitter are short-circuited, i.e., those qualities (properties) are determined. After this, an intermediate insulating film is formed.
According to the quality determination, via holes formed in the intermediate insulating film for the cell blocks are filled with polyimide solution dropped therein by a dispenser or the like. Accordingly, two-layered wiring members are provided to connect only the first gate wiring members of the non-defective cell blocks with the second layer gate wiring member and isolating the first gate wiring member of the defective cell block from the second gate wiring member to short the same to source electrodes. According to this method, even when the cell blocks includes some defective blocks, the IGBT can be composed of the non-defective cell blocks exclusively and can be normally operated. As a result, the rate of non-defective products can be prevented from dropping.
According to the method described above, however, the several cell blocks are determined on their quality in the course of the semiconductor wafer process, and then the multi-layered wiring structure must be formed for connecting the non-defective cell blocks exclusively with the gate bonding pad. Therefore, the process is very complicated. In addition, it is practically difficult (as the Publication fails to disclose the specific method) to decide the qualities of the cell blocks in the course of the semiconductor wafer process.
The present invention has been made in view of the above problems. An object of the present invention is to provide a semiconductor device and an insulated gate bipolar transistor that can prevent a rate of non-defective products from decreasing and be manufactured by a simple semiconductor wafer process even when the chip size of the semiconductor device is enlarged.
According to the present invention, briefly, a semiconductor device is composed of a semiconductor substrate, a plurality of cell blocks provided on the semiconductor substrate, a plurality of gate electrodes electrically independent of one another and respectively provided in the cell blocks, and a plurality of gate pads provided on the semiconductor substrate and respectively connected with the gate electrodes.
According to this construction, each of the cell blocks can be determined on whether it is defective or not readily by utilizing the gate pads. Then, only gate pads of non-defective cell blocks can be connected with a gate terminal provided outside of the semiconductor substrate. As a result, even when the semiconductor device includes a defective cell block, the semiconductor device can be operated normally, and a rate of non-defective products is prevented from dropping even when a chip size is enlarged. Incidentally, the gate pad of the defective cell block can be connected with one of a ground potential, an emitter pad, and a source pad.
Preferably, a plurality of marks are provided on the semiconductor substrate for discriminating whether the cell blocks are defective. Accordingly, the discrimination of whether the cell blocks are defective becomes easy. The semiconductor device can have a pad having an emitter potential, and the gate pad of the defective cell block can be connected with the pad. In this case, for example, a ground terminal needs not be provided outside of the semiconductor substrate by a lead frame or the like, resulting in size reduction and low manufacturing cost.